MAX19713ETN+T【PDF 18/37 页】IC ANLG FRNT END 56-TQFN

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MAX19713

Figure 6. Serial-Interface Timing Diagram

tCSW

tCS

LSB

tCL

tCP

tCH

tDH

tDS

MSB

tCSS

SCLK

DIN

CS/WAKE

10-Bit, 45Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________

QSPI is a trademark of Motorola, Inc.

Figure 7. Mode-Recovery Timing Diagram

CS/WAKE

SCLK

DIN

16-BIT SERIAL DATA INPUT

AD0–AD9

ID/QD

DAC ANALOG OUTPUT

SETTLES TO 10 LSB ERROR

ADC DIGITAL OUTPUT SINAD

SETTLES TO WITHIN 1dB

tWAKE,SD,ST_ TO Rx MODE OR tENABLE,RX

tWAKE,SD,ST_ TO Tx MODE OR tENABLE,TX

MAX19713 enters the power mode determined by the

WAKEUP-SEL register, however, all other settings (Tx

DAC offset, Tx DAC common-mode voltage, aux-DAC

settings, aux-ADC state) are restored to their values

prior to shutdown.

The only SPI line that is monitored by the MAX19713

during shutdown is

CS/WAKE. Any information transmit-

ted to the MAX19713 concurrent with the

CS/WAKE

wake-up pulse is ignored.

SPI Timing

The serial digital interface is a standard 3-wire connection

(

CS/WAKE, SCLK, DIN) compatible with SPI/QSPI/

MICROWIRE/DSP interfaces. Set

CS/WAKE low to enable

the serial data loading at DIN or output at DOUT.

Following a

CS/WAKE high-to-low transition, data is shift-

ed synchronously, most significant bit first, on the rising

edge of the serial clock (SCLK). After 16 bits are loaded

into the serial input register, data is transferred to the latch

when

CS/WAKE transitions high. CS/WAKE must transi-

tion high for a minimum of 80ns before the next write

sequence. SCLK can idle either high or low between tran-

sitions. Figure 6 shows the detailed timing diagram of the

3-wire serial interface.

Mode-Recovery Timing

Figure 7 shows the mode-recovery timing diagram.

tWAKE is the wake-up time when exiting shutdown, idle,

or standby mode and entering Rx, Tx, or FD mode.

tENABLE is the recovery time when switching between

either Rx or Tx mode. tWAKE or tENABLE is the time for

the Rx ADC to settle within 1dB of specified SINAD per-

formance and Tx DAC settling to 10 LSB error. tWAKE

and tENABLE times are measured after the 16-bit serial

command is latched into the MAX19713 by a

CS/WAKE

transition high. In FAST mode, the recovery time is 0.1s

to switch between Tx or Rx modes.

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